Efficient Techniques for Multiple Fault Test Generation

نویسندگان

  • Rikiya Nishigaya
  • Kom Kinoshita
چکیده

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived Experimental result for benchmark circuits shows the effectiveness of using the techniques.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Experimental Study of Scan Based Transition Fault Testing Techniques

The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and...

متن کامل

Directed Test Generation for Improved Fault Localization

Fault-localization techniques that apply statistical analyses to execution data gathered from multiple tests are quite effective when a large test suite is available. However, if no test suite is available, what is the best approach to generate one? This paper investigates the fault-localization effectiveness of test suites generated according to several test-generation techniques based on comb...

متن کامل

On the generation of test patterns for multiple faults

This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation th...

متن کامل

Simulation Based Sequential Circuit Automated Test Pattern Generation

The aim with this paper is to design a high efficient sequential ATPG on single stack-at fault model. A new approach for sequential circuit test generation is proposed in this paper. With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or faul...

متن کامل

Diagnostic test generation for sequential circuits

Efficient diagnosis of faults in VLSI circuits requires high quality diagnostic test sets. In this work, novel techniques for diagnostic test generation are proposed that require significantly less time than previous methods. The set of fault pairs left undistinguished by a detection-oriented test set is first filtered to target only testable faults. Then diagnostic test generation is performed...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2004